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| Author(s): |
Thiago Massariolli Sigrist
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | Campinas, SP. |
| Institution: | Universidade Estadual de Campinas (UNICAMP). Instituto de Computação |
| Defense date: | 2007-02-28 |
| Examining board members: |
Rodolfo Jardim de Azevedo;
Edward David Moreno Ordonez;
Ricardo de Oliveira Anido
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| Advisor: | Rodolfo Jardim de Azevedo |
| Abstract | |
The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure specifications and synthesizable RTL (Register Transfer Level ) descriptions, making the complexity of such systems more manageable. Considering that those systems usually have microprocessors as main modules, it is desirable to use architecture description languages (ADLs) like ArchC and its toolkit to model those processors and generate simulator modules for them in a fraction of the time usually spent in that task. However, ArchC, in its previous version, 1.6, has limitations for that use, since the simulators it generates are self-contained, thus hard to integrate to TLM system-level models. This work consists in remodelling ArchC and its acsim tool, adding this ability of integration to its functional interpreted simulators, leading to version 2.0 of ArchC (AU) | |