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| Author(s): |
Thiago Borges Abdnur
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | Campinas, SP. |
| Institution: | Universidade Estadual de Campinas (UNICAMP). Instituto de Computação |
| Defense date: | 2012-11-12 |
| Examining board members: |
Rodolfo Jardim de Azevedo;
Henrique Cota de Freitas;
Guido Costa Souza de Araújo
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| Advisor: | Rodolfo Jardim de Azevedo |
| Abstract | |
As processors design shift towards multicore architectures, new challenges arise to increase the core to core communication efficiency. Despite the potential huge performance impact, the number of papers focusing on this problem is limited. In this project, we define a communication model, adding three new instructions to the SPARCv8 instruction set, to allow different cores to communicate directly, without the shared memory and lock latencies. We implemented the model inside the LEON3 VHDL and evaluated it using synthetic benchmarks like producer-consumer and pipeline. To make the FPGA prototype timings more realistic, we also implemented a new memory timer so that it keeps the processor-memory speed ratio closer to real values. We also created the basic compiler support for these new instructions through intrinsic, converted to inline assembly in C code. Our overall results improve the performance from 3% to up to 70 times faster (AU) | |
| FAPESP's process: | 09/12853-2 - Development of an efficient solution for SPARCv8 processors intercommunication. |
| Grantee: | Thiago Borges Abdnur |
| Support Opportunities: | Scholarships in Brazil - Master |