CV Lattes
Universidade de São Paulo (USP). Escola Politécnica (EP) (Institutional affiliation from the last research proposal) Birthplace: Brazil
bachelor's from Centro Universitário da FEI (2011). Has experience in Electric Engineering, focusing on Eletronic. Studied Masters in Electrical Engineering in the field of Integrated Electronic Devices at Centro Universitário da FEI (2014) and obtained the PhD. Degree in Electrical Engineering in the field of Integrated Electronic Devices at Escola Politécnica da USP (2017) (Source: Lattes Curriculum)
| News published in Agência FAPESP Newsletter about the researcher |
| More itemsLess items |
| TITULO |
| Articles published in other media outlets ( ): |
| More itemsLess items |
| VEICULO: TITULO (DATA) |
| VEICULO: TITULO (DATA) |
With the continuous devices scaling, the fabrication CMOS technology, that actually is reaching nanometer scales, it has encountered some problems as the short channel effects. As an alternative for this technology, industries have changed the conventional CMOS technology by the silicon-on-insulator (SOI) technology. However, for dimensions below 22nm this technology has also been shown t…
As devices are scaled down, the charge control in the channel region becomes more difficult. Silicon-On-Insulator (SOI) multiple gate devices appear as an alternative to replace planar-transistor, as it provides better charge control and, consequently, higher short-channel effects (SCE) immunity. Besides the improved SCE control, it is known that SOI technology presents a better response …
In order to continuing scaling devices, new technologies have been studied as an alternative to conventional CMOS. One of devices that can overcome the limitations of MOSFET transistors is the Tunnel-FET (TFET) that can provide very low off state current and a subthreshold swing lower than the 60 mV/dec at room temperature, the theoretical limit for MOS technology. In order to improve the…
| 2 / 2 | Completed scholarships in Brazil |
| 1 / 1 | Completed scholarships abroad |
| 3 / 3 | All Scholarships |
| Associated processes | |