ITAP: Idle-Time-Aware Power Management for GPU Execution Units

Author(s)

Sadrosadati, Mohammad ^[1] ; Ehsani, Seyed Borna ^[1] ; Falahati, Hajar ^[2] ; Ausavarungnirun, Rachata ^[3] ; Tavakkol, Arash ^[4] ; Abaee, Mojtaba ^[2] ; Orosa, Lois ^[4] ; Wang, Yaohua ^[4] ; Sarbazi-Azad, Hamid ^{[2, 1]} ; Mutlu, Onur ^[4]

Affiliation

^[1] Sharif Univ Technol, Dept Comp Engn, Tehran - Iran

^[2] IPM, Inst Res Fundamental Sci, Sch Comp Sci, Tehran - Iran

^[3] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 - USA

^[4] Swiss Fed Inst Technol, Dept Comp Sci, Syst Grp, Zurich - Switzerland

• Document type: Journal article
• Source: ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION; v. 16, n. 1 MAR 2019.
• Web of Science Citations: 0

Abstract

Graphics Processing Units (GPUs) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUs suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU-the execution units-frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of execution units actually comes from short but frequent stalls, leaving little potential for common power saving techniques, such as power-gating. In this article, we propose ITAP, a novel idle-time-aware power management technique, which aims to effectively reduce the static energy consumption of GPU execution units. By taking advantage of different power management techniques (i.e., power-gating and different levels of voltage scaling), ITAP employs three static power reduction modes with different overheads and capabilities of static power reduction. ITAP estimates the idle period length of execution units using prediction and peek-ahead techniques in a synergistic way and then applies the most appropriate static power reduction mode based on the estimated idle period length. We design ITAP to be power-aggressive or performance-aggressive, not both at the same time. Our experimental results on several workloads show that the power-aggressive design of ITAP outperforms the state-of-the-art solution by an average of 27.6% in terms of static energy savings, with less than 2.1% performance overhead. However, the performance-aggressive design of ITAP improves the static energy savings by an average of 16.9%, while keeping the GPU performance almost unaffected (i.e., up to 0.4% performance overhead) compared to the state-of-the-art static energy savings mechanism. (AU)

• FAPESP's process: 16/18929-4 - Speculative techniques for reducing the memory bottleneck problem
• Grantee: Lois Orosa Nogueira
• Support Opportunities: Scholarships abroad - Research Internship - Post-doctor