| Full text | |
| Author(s): |
Salamanca, Juan
;
IEEE
Total Authors: 2
|
| Document type: | Journal article |
| Source: | 2022 21ST INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING (ISPDC 2022); v. N/A, p. 8-pg., 2022-01-01. |
| Abstract | |
Speculative Taskloop (STL) is a loop parallelization technique that takes the best of Task-based Parallelism and Thread-Level Speculation to speed up loops with may loop-carried dependencies that were previously difficult for compilers to parallelize. Previous studies show the efficiency of STL when implemented using Hardware Transactional Memory and the advantages it offers compared to a typical DOACROSS technique such as OpenMP ordered. This paper presents a performance comparison between STL and a previously proposed technique that implements Thread-Level Speculation (TLS) in the for worksharing construct (FOR-TLS) over a set of loops from cbench and SPEC2006 benchmarks. The results show interesting insights on how each technique can be more appropriate depending on the characteristics of the evaluated loop. Experimental results reveal that by implementing both techniques on top of HTM, speed-ups of up to 2.41x can be obtained for STL and up to 2x for FOR-TLS. (AU) | |
| FAPESP's process: | 18/07446-8 - Integrating Speculative Execution to Loop and Task-based Parallelization |
| Grantee: | Juan Jesús Salamanca Guillén |
| Support Opportunities: | Scholarships in Brazil - Post-Doctoral |
| FAPESP's process: | 18/15519-5 - Performance optimizations for multicore architectures |
| Grantee: | Alexandro José Baldassin |
| Support Opportunities: | Research Grants - Young Investigators Grants - Phase 2 |
| FAPESP's process: | 20/01665-0 - Integrating speculative execution to task parallelism |
| Grantee: | Juan Jesús Salamanca Guillén |
| Support Opportunities: | Scholarships abroad - Research Internship - Post-doctor |