Performance optimizations for multicore architectures

• Grant number: 18/15519-5
• Support Opportunities: Research Grants - Young Investigators Grants - Phase 2
• Duration: May 01, 2019 - April 30, 2025
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Alexandro José Baldassin
• Grantee: Alexandro José Baldassin
• Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
• Associated researchers: Aleardo Manacero Junior ; Guido Costa Souza de Araújo
• Associated research grant: 11/19373-6 - Understanding and exploiting energy/performance tradeoffs in concurrent algorithms, AP.JP
• Associated scholarship(s): 24/13785-0 - Programming and Performance Tradeoffs in Persistent Memory Systems, BP.IC; 24/13771-0 - Memory Allocation on NUMA Systems with Persistent Memory, BP.IC; 24/02372-7 - Using Persistent Memory to Accelerate Large Language Model Inference, BP.MS; + associated scholarships 23/10128-6 - Performance analysis of undo and redo logs in persistent memory systems, BP.IC; 23/04969-8 - Optimizing Data Structures for Persistent Memory, BP.MS; 23/04971-2 - Optimizing the Performance of Persistent Memory using Hardware Transactions, BP.PD; 23/05019-3 - A Comparison of Programming Interfaces for Persistent Memory, BP.IC; 23/05032-0 - Evaluating the Impact of Memory Allocation in Persistent Memory Systems, BP.IC; 22/11704-8 - Efficient Handling of Large Heap Allocation in Persistent Hardware Transactional Memory Systems, BP.MS; 21/05440-5 - Investigating the programmability aspects of persistent memory systems, BP.IC; 20/15402-0 - Characterizing the performance loss of software transactional memory systems on a NUMA architecture, BP.IC; 19/10471-7 - Making the most out of hardware transactional memory, BE.PQ; 18/07446-8 - Integrating Speculative Execution to Loop and Task-based Parallelization, BP.PD - associated scholarships

Abstract

Multicore machines are ubiquitous nowadays and the tendency is for semiconductor companies to keep adding more and more cores into their new microprocessors. Unfortunately, support for programming these highly parallel machines have not kept pace and we are left with underutilized computer systems. The big challenge facing the industry today is how to ease the life of programmers in writing parallel code by creating adequate software and hardware. What makes parallel programming so hard is that programmers are faced with two simultaneous demanding goals: the code must be correct and efficient, both performance and energy-wise, as the number of cores per chip scales. Writing parallel code is not hard per se, but writing parallel code that can achieve high performance and scalability is far from trivial.In a broad sense, this research project aims at investigating performance optimizations for multicore microprocessors so that programmers can more easily write parallel code and still benefit from current multicore machines. In particular, this project seeks to investigate optimization opportunities both at the programmer level, by providing diagnostic and profiling tools along with powerful language constructs, and at the code level, by devising optimization techniques for compilers and runtime. A clear contribution of this proposal is to enable average programmers to make the most out of current multicore-based systems, as well as to deliver automatic techniques to improve performance of parallel code. (AU)

Scientific publications

(8)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

BALDASSIN, ALEXANDRO; BARRETO, JOAO; CASTRO, DANIEL; ROMANO, PAOLO. Persistent Memory: A Survey of Programming Support and Implementations. ACM COMPUTING SURVEYS, v. 54, n. 7, SEP 2021. (19/10471-7, 18/15519-5)

SALAMANCA, JUAN; BALDASSIN, ALEXANDRO; KLEMM, M; DESUPINSKI, BR; KLINKENBERG, J; NETH, B. Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP. OPENMP IN A MODERN WORLD: FROM MULTI-DEVICE SUPPORT TO META PROGRAMMING, v. 13527, p. 15-pg., 2022-01-01. (18/07446-8, 18/15519-5, 20/01665-0)

SALAMANCA, JUAN; IEEE. Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory. 2022 21ST INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING (ISPDC 2022), v. N/A, p. 8-pg., 2022-01-01. (18/07446-8, 18/15519-5, 20/01665-0)

SALAMANCA, JUAN; BALDASSIN, ALEXANDRO; FAN, X; DESUPINSKI, BR; SINNEN, O; GIACAMAN, N. A Proposal for Supporting Speculation in the OpenMP taskloop Construct. OPENMP: CONQUERING THE FULL HARDWARE SPECTRUM, IWOMP 2019, v. 11718, p. 16-pg., 2019-01-01. (18/15519-5, 18/07446-8)

BALDASSIN, ALEXANDRO; MURARI, RAFAEL; DE CARVALHO, JOAO P. L.; ARAUJO, GUIDO; CASTRO, DANIEL; BARRETO, JOAO; ROMANO, PAOLO; MALAWSKI, M; RZADCA, K. NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory. EURO-PAR 2020: PARALLEL PROCESSING, v. 12247, p. 16-pg., 2020-01-01. (13/08293-7, 18/15519-5, 19/10471-7, 16/15337-9)

DE CARVALHO, JOAO P. L.; HONORIO, BRUNO C.; BALDASSIN, ALEXANDRO; ARAUJO, GUIDO; IEEE. Improving Transactional Code Generation via Variable Annotation and Barrier Elision. 2020 IEEE 34TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM IPDPS 2020, v. N/A, p. 10-pg., 2020-01-01. (19/04536-9, 13/08293-7, 16/15337-9, 18/15519-5)

CASTRO, DANIEL; BALDASSIN, ALEXANDRO; BARRETO, JOAO; ROMANO, PAOLO; USENIX ASSOC. SPHT: Scalable Persistent Hardware Transactions. PROCEEDINGS OF THE 19TH USENIX CONFERENCE ON FILE AND STORAGE TECHNOLOGIES (FAST '21), v. N/A, p. 15-pg., 2021-01-01. (19/10471-7, 18/15519-5)

SALAMANCA, JUAN; BALDASSIN, ALEXANDRO; MCINTOSHSMITH, S; DESUPINSKI, BR; KLINKENBERG, J. Improving Speculative taskloop in Hardware Transactional Memory. OPENMP: ENABLING MASSIVE NODE-LEVEL PARALLELISM, IWOMP 2021, v. 12870, p. 15-pg., 2021-01-01. (18/15519-5, 18/07446-8)