Design Space Exploration for CNN Offloading to FPGAs at the Edge

Author(s)

Korol, Guilherme ; Jordan, Michael Guilherme ; Rutzig, Mateus Beck ; Castrillon, Jeronimo ; Schneider Beck, Antonio Carlos ; Kastensmidt, F ; Reis, R ; Todri-Sanial, A ; Li, H ; Metzler, C

• Document type: Journal article
• Source: 2023 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, ISVLSI; v. N/A, p. 6-pg., 2023-01-01.

Abstract

AI-based IoT applications relying on heavy-load deep learning algorithms like CNNs challenge IoT devices that are restricted in energy or processing capabilities. Edge computing offers an alternative by allowing the data to get offloaded to so-called edge servers with hardware more powerful than IoT devices and physically closer than the cloud. However, the increasing complexity of data and algorithms and diverse conditions make even powerful devices, such as those equipped with FPGAs, insufficient to cope with the current demands. In this case, optimizations in the algorithms, like pruning and early-exit, are mandatory to reduce the CNNs computational burden and speed up inference processing. With that in mind, we propose ExpOL, which combines the pruning and early-exit CNN optimizations in a system-level FPGA-based IoT-Edge design space exploration. Based on a user-defined multi-target optimization, ExpOL delivers designs tailored to specific application environments and user needs. When evaluated against state-of-the-art FPGA-based accelerators (either local or offloaded), designs produced by ExpOL are more power-efficient (by up to 2x) and process inferences at higher user quality of experience (by up to 12.5%). (AU)

• FAPESP's process: 21/06825-8 - ADAPTT: providing resource efficiency in traffic classification through the synergistic and adaptive use of FPGAs and CNNs
• Grantee: Antonio Carlos Schneider Beck Filho
• Support Opportunities: Regular Research Grants