| Author(s): |
de Carvalho, Dionisio
;
Sanches, Bruno
;
De Carvalho, M.
;
Van Noije, Wilhelmus
;
IEEE
Total Authors: 5
|
| Document type: | Journal article |
| Source: | 2018 IEEE 19TH LATIN-AMERICAN TEST SYMPOSIUM (LATS); v. N/A, p. 6-pg., 2018-01-01. |
| Abstract | |
Technology scaling made possible to increase IC capabilities from one node to the next by adding more transistors within the same die area while keeping a low pin count. As a consequence, test complexity increased exponentially, requiring engineers to use not only better test pattern generation software, but also powerful and expensive Automatic-Test-Equipments (ATE), usually not viable and accessible for small fabless startups and universities. In this work, we propose a low-cost and flexible ATE intended for manufacturing tests of the digital part of a multi-million gate industrial mixed signal ASIC produced in a 130nm technology that will be used at CERN in the ALICE experiment. The proposed ATE was built upon a ready-to-use platform including an embedded ARM-based processor and a FPGA to effectively apply the test vectors via the Device-UnderTest (DUT) scan chains in a feasible time and viable cost without the need for a PC. The ATE was operated to execute in-series manufacturing tests on two versions of the SAMPA chip, allowing identifying on-silicon defects. (AU) | |
| FAPESP's process: | 14/12664-3 - Development of scientific instrumentation for the ALICE experiment at the LHC-CERN |
| Grantee: | Wilhelmus Adrianus Maria van Noije |
| Support Opportunities: | Special Projects |
| FAPESP's process: | 13/06885-4 - Design of a signal adquisition and digital processing ASIC for time projection chamber of ALICE experiment |
| Grantee: | Wilhelmus Adrianus Maria van Noije |
| Support Opportunities: | Regular Research Grants |