| Full text | |
| Author(s): |
Hernandez, Hugo
;
Carvalho, Dionisio
;
Sanches, Bruno
;
Severo, Lucas C.
;
Van Noije, Wilhelmus
;
IEEE
Total Authors: 6
|
| Document type: | Journal article |
| Source: | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS); v. N/A, p. 4-pg., 2017-01-01. |
| Abstract | |
This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes a feedback control which reduces the commonmode voltage variations in terms of the VDS voltage of the bias transistor, and an enable/disable operation mode, which minimizes the power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to design the receiver circuit being robust to transient commonmode variations with low power consumption and high speed. The experimental DC power consumption of the transceiver is 4.6 mW at 1.25V power supply, where 1.1 mW is consumed by the receiver and 3.5 mW by the transmitter. The eye diagram proves the proper dynamic operation of the circuit until a data rate of 1.2Gbps. (AU) | |
| FAPESP's process: | 14/12664-3 - Development of scientific instrumentation for the ALICE experiment at the LHC-CERN |
| Grantee: | Wilhelmus Adrianus Maria van Noije |
| Support Opportunities: | Special Projects |
| FAPESP's process: | 13/06885-4 - Design of a signal adquisition and digital processing ASIC for time projection chamber of ALICE experiment |
| Grantee: | Wilhelmus Adrianus Maria van Noije |
| Support Opportunities: | Regular Research Grants |