| Full text | |
| Author(s): |
do Rosario, Vanderson Martins
;
Hato, Mario Mikio
;
Azevedo, Rodolfo
;
Borin, Edson
;
Bianchini, CD
;
DeSouza, PSL
;
DeBarros, COF
;
Ferreira, RAC
Total Authors: 8
|
| Document type: | Journal article |
| Source: | 2018 SYMPOSIUM ON HIGH PERFORMANCE COMPUTING SYSTEMS (WSCAD 2018); v. N/A, p. 8-pg., 2018-01-01. |
| Abstract | |
Interpretation is a simple and portable technique that enables emulation of instruction set architectures (ISAs). Even though other techniques, such as binary translation, still provide superior emulation performance, interpreters are easier to implement and debug. Because of that, they are often used to complement binary translation techniques or to design reference instruction set simulators (ISS). In this work, we characterize the main causes of overhead in an interpreter and present a methodology to analyze and optimize interpreters code. The methodology was designed having in mind the most common practices in the development of interpreters, the operation of modern processors architectures and memory hierarchy. Finally, to evidence the importance of the methodology we present a case study in which we used it to optimize an interpreter-based ISS, improving its performance by 48%. (AU) | |
| FAPESP's process: | 13/08293-7 - CCES - Center for Computational Engineering and Sciences |
| Grantee: | Munir Salomao Skaf |
| Support Opportunities: | Research Grants - Research, Innovation and Dissemination Centers - RIDC |