Single nanofabrication step of low series resistance nanowire-based devices for giant piezoresistance characterization

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Author(s):	Chi, Kung Shao ; Spejo, Lucas Barroso ; Minamisawa, Renato A. ; dos Santos, Marcos V. Puydinger Total Authors: 4
Document type:	Journal article
Source:	2024 38TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES, SBMICRO 2024; v. N/A, p. 4-pg., 2024-01-01.
Abstract
In this work, we aim to fabricate strained silicon nanowires (sSiNWs) to study their electric mobility and giant piezoresistance. Through techniques compatible with the CMOS technology, individual nanowires (NWs) were fabricated from strained silicon-on-insulator (sSOI) thin films with 0.8% biaxial strain. Subsequently, the buried oxide (BOX) was removed from the SOI film, thus suspending the NWs, and the new boundary condition of its surface induces mechanical stress amplification, now uniaxial in the NW longitudinal direction. The proposal is to stress the NWs to levels higher than those employed in industry and, hence, fabricate prototypes using a single-step fabrication protocol, yet with an optimized contact resistance. Parameter optimization can further result in the fabrication of MOSFETs based on a single ultra-strained NW in gate-all-around (GAA) topology, as well as chemical and physical sensors for various technological applications. (AU)

FAPESP's process:	22/16809-2 - Fabrication and characterization of MOSFET transistors based on ultra-strained silicon nanowires
Grantee:	Kung Shao Chi
Support Opportunities:	Scholarships in Brazil - Master