| Full text | |
| Author(s): |
Silva, V. C. P.
;
Ribeiro, A. R.
;
Martino, J. A.
;
Veloso, A.
;
Horiguchi, N.
;
Agopian, P. G. D.
Total Authors: 6
|
| Document type: | Journal article |
| Source: | Solid-State Electronics; v. 225, p. 4-pg., 2025-01-24. |
| Abstract | |
This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/ dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (AV) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, V EA and AV, in the reverse mode shows better gmsat, SS sat and fT. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (fT) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, AV = 28 dB and fT = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and fT = 3.7 GHz in reverse mode. (AU) | |
| FAPESP's process: | 20/04867-2 - High energy physics and instrumentation with the LHC-CERN |
| Grantee: | Marcelo Gameiro Munhoz |
| Support Opportunities: | Special Projects |