Development of all-printed vertical field-effect transistor

• Grant number: 18/02037-2
• Support type: Scholarships in Brazil - Doctorate
• Effective date (Start): August 01, 2018
• Effective date (End): February 28, 2021
• Field of knowledge: Engineering - Materials and Metallurgical Engineering
• Principal Investigator: Neri Alves
• Grantee: Gabriel Leonardo Nogueira
• Home Institution: Faculdade de Ciências e Tecnologia (FCT). Universidade Estadual Paulista (UNESP). Campus de Presidente Prudente. Presidente Prudente , SP, Brazil

Abstract

High-performance printed transistors are necessary to making printed electronic a reality. To achieve this goal, there are two main options: the study of materials that forms the device, and the improvement of device architecture. Oxide semiconductors, among them zinc oxide (ZnO), is a class of materials with good mobility that have been used as semiconductor layer in printed transistors. About promising architectures, vertical field-effect transistor (VFET) stands out. In VFETs, the layers are vertically stacked in such a way that semiconductor layer separates source and drain electrodes, where the channel length is given by the thickness of semiconductor thin-film. The main challenge of VFET is the development of intermediate electrode, which must have good lateral conductivity and permeability to gate electric field. This project aims the development of printed VFETs, which require the study of each layers that forms the device. The main steps are the fabrication of printed intermediate electrode based on conductive networks, as carbon nanotube and silver nanowire, and the use of ZnO and aluminum oxide (Al2O3) as semiconductor and dielectric, respectively. The use of spray pyrolysis to obtain the intermediate electrode enables the percolation study of this conductive film by measurements in situ of electric resistance and capacitance. To perform a theoretical study of percolation, a model to simulate the deposition process will be develop. Besides, the design of experiments (DOE) will be applied in the main steps to optimize the VFET fabrication.