Hybrid Network-on-chips (hoc) for safe integrated electronic systems

• Grant number: 12/20312-4
• Support Opportunities: Regular Research Grants
• Start date: April 01, 2013
• End date: March 31, 2015
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits
• Principal Investigator: Marius Strum
• Grantee: Marius Strum
• Host Institution: Escola Politécnica (EP). Universidade de São Paulo (USP). São Paulo , SP, Brazil
• Associated researchers: Martha Johanna Sepúlveda Flórez ; Ricardo Pires ; Wang Jiang Chau

Abstract

Hw-Sw electronic systems, developed as single chips integrated circuits, known as system-on-chip (SoC), are characterized (from the Hw perspective) by their high integration level. They are able to assemble a large quantity and variety of components on a single chip. Distributed electronic systems may be implemented as multi-processor SoCs (MPSoC). These are commonly multi-application systems that require a high degree of resource sharing. The Hw design is usually decomposed into 2 concurrent and interdependent designs: the computation structure and the communication structure (CS). The most common CS are hierarchical buses (Hbus) and network-on-chips (NoC). Hybrid communication structures, known as hybrid-on-chip (HoC) have been becoming increasingly popular. They merge buses and NoCs into a single CS which allows to optimize the resulting system's behavior for their different traffic conditions. HoCs have been considered as the most adequate communication structures for the 3D SoCs (3 dimensions), a new technology that allows to vertically integrate components in a single chip. The EC performance's influence over the full system's performance has been increasing due to the increase in number and complexity of components and applications that are integrated on a single SoC (MPSoC). Besides the performance, the EC is also responsible for attending different qualities of service (QoS) required by the applications. Another increasingly important issue concerns the critical information that is captured, stored and processed in a system. This fact implies that security has become another critical design requirement. Security can be implemented either in the computation or in the communication structure. Including security services in the EC is attractive due to its possibility to: 1) monitor the transmitted information; 2) detect violations; 3) block attacks; and 4) offer information to diagnose and activate defense and recovery mechanisms. A recently developed concept called quality of security services - QoSS permits to include the system's security as a further dimension of its quality of service by accepting the possibility to provide different protection levels. The EC design requires the development of several models at different abstraction levels to be used during different design steps. Such models are highly parameterizable leading to a large variety of EC instances (EC configurations). The set of all possible configurations is designated as "solution space". In this project we propose 2 objectives. The first consists of developing two models of a QoSS-HoC: 1- A TLM-SystemC high level model that allows to perform functional simulations at the first stages of a SoC design in order to validate the EC's behavior as well as to realize performance estimations; 2- A synthesizable VHDL low level model that serves to evaluate the communication structure's performance when fitted on a commercial FPGA. However, finding an EC instance in the solution space that simultaneously satisfies the functionality, performance, quality of service and security requirements for each application (or applications set) is not a trivial task. Our second objective consists of proposing a design methodology that allows to quickly search the solution space looking for one that satisfies the design's requirements (specifications). (AU)