| Grant number: | 13/18794-3 |
| Support Opportunities: | Scholarships in Brazil - Master |
| Start date: | March 01, 2014 |
| End date: | February 28, 2015 |
| Field of knowledge: | Physical Sciences and Mathematics - Computer Science - Computer Systems |
| Principal Investigator: | Edson Borin |
| Grantee: | Guilherme Guaglianoni Piccoli |
| Host Institution: | Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil |
Abstract The use of ccNUMA architectures (cache coherent Non-Uniform Memory Access) over SMP (Symmetric Multiprocessing) is becoming increasingly common. The main advantage of ccNUMA is that memory accesses are distributed between controllers, which communicate with one another using an interconnect network, so the pressure on the central bus present in SMP is relieved - these architectures are known for being subject to concurrency problems in memory access as the number of processors grows. Although parallel programs developed with SMP architectures in mind can run on ccNUMA without modifications, one common problem in this approach is slowdown in performance of programs which have too many main memory accesses, because they can be slow to perform - if data is in a bank connected to a memory controller "far" from the processor which is using it, the access will be variable and could be much slower than if the data is in a memory controller connected to the processor that is using it. Many techniques have been proposed to deal with this problem, from better programming approaches - with ccNUMA peculiarities in mind - to dynamic memory pages migration, in general implemented in the scope of operating systems. Our purpose is to present a code optimization model that can dynamically migrate memory pages to controllers near the processors that are using data in those pages, relying on a simple dynamic loop iteration number predictor. We use the powerful and adaptive LLVM toolchain to implement our model. (AU) | |
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