OMPSoC: Heterogeneous Optical Multiprocessor System on Chip Modeling

• Grant number: 14/01642-9
• Support Opportunities: Scholarships in Brazil - Doctorate
• Start date: May 01, 2014
• End date: February 28, 2018
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Rodolfo Jardim de Azevedo
• Grantee: Jorge Luis Gonzalez Reano
• Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil

Abstract

Multi-Processor System on Chip (MPSoC) designers have adopted diverse high level hardware modeling methodologies and hardware reusable module description to reduce complexity and effort during implementation of integrated system projects caused by the continuous increase in device integration. Nowadays, those devices are using buses to communicate in the intrachip level, whose implementation guarantees interoperability between the elements of the MPSoC, however it has low scalability and low module re-usability. Therefore there is a growing interest in the industry to incorporate Network on chips (NoC), allowing the connection of many processor elements within the same chip (more than 40) differently than buses.This works aims to model heterogeneous CPU+GPU simulation platforms with NoC communication structures to link the internal elements using high level description hardware languages and to evaluate their performance analyzing metrics known from previous works. This work also explores Network Level Photonic communication device modeling which form an Optical Network on Chip (ONoC), motivated by the visible trend on 3D multilayer chip fabrication and to exploit its advantages on chip energy consumption. Are expected to implement simulation platforms which help decision making on the MPSoC project design flow and to obtain parameters to compare with the results of previous works.The SystemC-TLM language will be used as the basis for electrical and optical hardware modeling. Diverse processor models such as ARM, MIPS, PowerPC, SPARC will be used an will be evaluated the implementation of CPU+GPU models. One of the challenges of this work will be the integration of CPU+GPU models with the previously mentioned processor models. The main challenge is the Photonic device modeling and its integration with electrical processor models.The SystemC-TLM language will be used as the basis for electrical and optical hardware modeling. Diverse processor models such as ARM, MIPS, PowerPC, SPARC will be used an will be evaluated the implementation of CPU+GPU models. One of the challenges of this work will be the integration of CPU+GPU models with the previously mentioned processor models. Another important challenge is the Photonic device modeling and its integration with electrical processor models.

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

GONZALEZ, JORGE; PALMA, MAURICIO G.; HATTINK, MAARTEN; RUBIO-NORIEGA, RUTH; OROSA, LOIS; MUTLU, ONUR; BERGMAN, KEREN; AZEVEDO, RODOLFO. Optically connected memory for disaggregated data centers. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, v. 163, p. 13-pg., 2022-02-22. (13/08293-7, 14/01642-9)

CHIARELLI BUENO FILHO, JOSE EDUARDO; GONZALEZ REANO, JORGE LUIS; CHAU, WANG JIANG; BHATIA, K; ALIOTO, M; ZHAO, D; MARSHALL, A; SRIDHAR, R. Intra-chip Traffic Generation Under Autoregressive Models Based on Time Series Obtained by TLM Simulation. 2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), v. N/A, p. 6-pg., 2016-01-01. (14/01642-9)

GONZALEZ, JORGE; GAZMAN, ALEXANDER; HATTINK, MAARTEN; PALMA, MAURICIO G.; BAHADORI, MEISAM; RUBIO-NORIEGA, RUTH; OROSA, LOIS; GLICK, MADELEINE; MUTLU, ONUR; BERGMAN, KEREN; et al. Optically Connected Memory for Disaggregated Data Centers. 2020 IEEE 32ND INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD 2020), v. N/A, p. 8-pg., 2020-01-01. (13/08293-7, 14/01642-9)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

REANO, Jorge Luis Gonzalez. Oportunidades da fotônica em sistemas computacionais modernos. 2021. Doctoral Thesis - Universidade Estadual de Campinas (UNICAMP). Instituto de Computação Campinas, SP.