| Grant number: | 18/00687-0 |
| Support Opportunities: | Scholarships abroad - Research Internship - Master's degree |
| Start date: | February 28, 2018 |
| End date: | June 27, 2018 |
| Field of knowledge: | Physical Sciences and Mathematics - Computer Science - Computer Systems |
| Principal Investigator: | Alfredo Goldman vel Lejbman |
| Grantee: | Lucas Henrique Morais |
| Supervisor: | Rosa Maria Badia Sala |
| Host Institution: | Instituto de Matemática e Estatística (IME). Universidade de São Paulo (USP). São Paulo , SP, Brazil |
| Institution abroad: | Barcelona Supercomputing Center (BSC), Spain |
| Associated to the scholarship: | 17/02682-2 - Designing a task-centric manycore architecture, BP.MS |
Abstract The Task Scheduling Paradigm is a general technique for leveraging fine and coarse parallelism from applications of several domains with minimum impact on code readability, relying on the automatic inference of data dependencies among tasks. The performance of Task Parallel applications is thus correlated with the speed at which the underlying Task Scheduling System is able to detect such dependencies, something that is most critical for fine-granularity workloads, which cannot amortize scheduling overheads with long periods of useful computation. That being the case, several groups have recently been developing FPGA-accelerated Task Scheduling Systems - organizations where a software Task Scheduling Runtime is able to offload its bookkeeping computations to an FPGA-based accelerator, improving the ability of these systems of efficiently handling fine-grained tasks.Even though these FPGA-accelerated systems offer substantial gains over the software-only baseline, it is also true that FPGA-CPU communication bottlenecks prevent such designs from handling scenarios with either large number of cores or very fine-grained tasks. With that in mind, we propose the implementation of a Native Task Scheduling System - that is, a processor with native support for task scheduling embedded into its architecture - with the goal of substantially reducing these communications overheads.More specifically, we would like to embed the HW logic of Picos, a mature Task Scheduling Accelerator developed by the Barcelona Supercomputing Center (BSC), into Rocket Chip, an open-source, silicon-proven, multi-core implementation of RISC-V. The ISA of the resulting system will then provide special instructions for Task Applications to interact with this Task Scheduling Logic, eliminating the need of a software mediator runtime and its associated overheads while, even more importantly, ruling out all FPGA-CPU communication latencies. (AU) | |
| News published in Agência FAPESP Newsletter about the scholarship: | |
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