Exploration of an FPGA-orientated hardware infrastructure for ultra-low latency DNN deployment

• Grant number: 19/05286-6
• Support Opportunities: Scholarships abroad - Research
• Start date: October 01, 2019
• End date: September 30, 2020
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Vanderlei Bonato
• Grantee: Vanderlei Bonato
• Host Investigator: Christos-Savvas Bouganis
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
• Institution abroad: Imperial College London, England

Abstract

The adoption of Deep Neural Networks on real time systems requires a special attention to the latency of the network inference stage. The signal propagation delay through layers strongly depends on memory organization, network connectivity balance, and on the level of computing parallelization along with the operations complexity. Recent works demonstrated promising results from design space exploration techniques for multi-objective metrics, considering latency, accuracy, and computational resources. However, when ultra low latency is desired the challenge remains since it does a strong pressure on computational resources requiring not only architectural improvements, but also further problem-orientated optimizations provided by highly customized hardware components. This research project aims to explore the conditions to enable ultra low latency deployments of CNN and LSTM-based models on FPGAs, having as case study the High Frequency Trading problem. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

BONATO, VANDERLEI; BOUGANIS, CHRISTOS-SAVVAS. Class-specific early exit design methodology for convolutional neural networks. APPLIED SOFT COMPUTING, v. 107, AUG 2021. (19/05286-6)