Adding native support for task scheduling to a RISC-V multi-core processor
Implementation of the Low-PHY functions of the 5G network structure in an FPGA-acc...
Custom heterogeneous hardware acceleration for high-performance computing applicat...
Custom heterogeneous hardware acceleration for high-performance computing applicat...
Dynamic Function Exchange in FPGAs to redefine multicore architectures at runtime.
Code snippets identification for pipeline processing in FPGA accelerators for hete...
Mapping and evaluation of parallel solution for stiff Ordinary differential equati...