Study and Electrical Characterization of triple gate SOI MOSFETs (SOI FinFETs).
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Author(s): |
Bernardo Goisman
Total Authors: 1
|
Document type: | Master's Dissertation |
Press: | São Paulo. |
Institution: | Universidade de São Paulo (USP). Escola Politécnica (EP/BC) |
Defense date: | 1996-05-21 |
Examining board members: |
Marius Strum;
Galdenoro Botura;
Max Gerken
|
Advisor: | Marius Strum |
Abstract | |
This text dewscribes an application specific integrated circuit design which executes the Cordic algorithm. The synthesized circuit is programmable. Six primitive functions can be calculated depending on 2 external control signals. These primitive functions can be used to generate a few elementary arithmetic functions. The combination of this chip with additional hardware permits to obtain other arithmetic functions as well as digital signal processing algorithms. The algorithm was descibed and verified through floating point simulations (Pascal) and fixed point simulation (Silage). After the algorithms validation, an architecture composed of 32 function blocks was manually synthesized. This architecture was described using the HILARICS/LOGMOS language and it was validated through RTL simulations. This architecture (schematic) was captured using the LOGIC III language of the OASIS system. The standard cell and function library (2µm CMOS) coupled to the Oasis system has been used for this purpose. The processors control unit was obtained through logic synthesis followed by technology mapping using the same OASIS system. Logic simulations validated the synthesized circuit. After placement and routing, the standard cell layout resulted in a chip with an área of 31.91 mm2 includignI/O cells. The chip has 120 pins and approximately 2000 standard cells. Timing verification showed a critical time smaller than 120ns. (AU) |