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| Author(s): |
Marcelo Antonio Pavanello
Total Authors: 1
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| Document type: | Doctoral Thesis |
| Press: | São Paulo. |
| Institution: | Universidade de São Paulo (USP). Escola Politécnica (EP/BC) |
| Defense date: | 2000-04-28 |
| Examining board members: |
João Antonio Martino;
Nelson Liebentritt de Almeida Braga;
Jader Alves de Lima Filho;
Sebastião Gomes dos Santos Filho;
Jacobus Willibrordus Swart
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| Advisor: | João Antonio Martino |
| Abstract | |
We present in this work the design, process fabrication and electrical characterization of a new structure to the SOI MOSFET, developed with the aim to alleviate the inherent parasitic bipolar effects in fully-depleted SOI transistors. The designof the structure is assisted by the physics of the parasitic bipolar action and by device numerical bidimensional simulations, resulting in a device with asymmetric channel doping profile. The device fabrication process is fully compatible withthe process flow used to fabricate conventional SOI MOSFETs. We obtained a device that presents significant improvements in the breakdown voltage and threshold voltage instability, due to the high electric field in the drain region, highertransconductance and reduced output conductance if compared to the conventional SOI MOSFETs. The performance of the proposed device in analog applications is also studied, showing the great potential to obtain high gain amplifiers with reducedpower consumption. (AU) | |