Advanced techniques for power modeling, analysis and optimization in digital systems

Author(s)

Felipe Vieira Klein

• Document type: Doctoral Thesis
• Press: Campinas, SP.
• Institution: Universidade Estadual de Campinas (UNICAMP). Instituto de Computação
• Defense date: 2009-10-21

Examining board members

Rodolfo Jardim de Azevedo; Luiz Claudio Villar dos Santos; Luigi Carro; Reinaldo Alvarenga Bergamaschi; Sandro Rigo

• Advisor: Guido Costa Souza de Araújo; Rodolfo Jardim de Azevedo

Abstract

The growing demand for features to be included into electronic devices, along with tight performance constraints, make power consumption one of the most important design constraints in the CAD/EDA design flow. The constant evolution of the semiconductor technology, observed in the last decades, has considerably increased the complexity of today's systems, which demand exorbitant computational resources. Unfortunately, the growing complexity leads to a higher power consumption which, in turn, has a number of undesired side effects, such as thermal issues and increased power density, thus compromising the overall circuit reliability. Hence, elaborated cooling solutions are required, increasing its final cost and compromising its time-to-market. Moreover, the large amounts of energy needed by portable devices substantially reduce their battery lifetime. The contributions of this thesis encompass two distinct topics within the so-called low-power design. The first one is related to RTL power macromodeling techniques. It is shown that conventional single-model techniques have intrinsic limitations that affect their accuracy. Then, a quantitative and qualitative analysis is conducted, pinpointing the limitations of several well-known techniques, followed by a demonstration that the adoption of a single technique may compromise the overall quality of the estimates. Subsequently, two novel multi-model power macromodeling techniques are proposed, which exploit the strengths of each single-model technique in order to optimize the accuracy of power estimation. The obtained results revealed substantial improvements in accuracy, which becomes 7 times better for the average errors, while the overall maximum estimation error is divided by 9. The second part of this thesis is related to a topic which is gaining much attention recently in the multi-core era: the concurrent programming paradigm widely known as transactional memory, which aims at making the task of creating concurrent software simpler. Although this is a rather active area, researchers have invariably focused on performance, leaving other metrics such as power and energy unattended. This work presents a detailed power analysis of a state-of-the-art STM (Software Transactional Memory) implementation, being the first one in this context. Moreover, a novel DVFS-based (Dynamic Voltage and Frequency Scaling) contention management strategy is proposed, which reduces the energy consumption by exploiting the slack available in applications displaying high bus contention (AU)

• FAPESP's process: 05/02565-9 - Power analysis/optimization of heterogeneous SoCs weighting hardware/software components
• Grantee: Felipe Vieira Klein
• Support Opportunities: Scholarships in Brazil - Doctorate