| Full text | |
| Author(s): |
Total Authors: 3
|
| Affiliation: | [1] Univ Sao Paulo, Inst Math & Comp Sci, Av Trabalhador Sao Carlense 400, Sao Carlos - Brazil
[2] Imperial Coll London, Dept Elect & Elect Engn, Exhibit Rd, London SW7 2BU - England
Total Affiliations: 2
|
| Document type: | Journal article |
| Source: | MICROPROCESSORS AND MICROSYSTEMS; v. 86, OCT 2021. |
| Web of Science Citations: | 0 |
| Abstract | |
High-level synthesis is a powerful tool for increasing productivity in digital hardware design. However, as digital systems become larger and more complex, designers have to consider an increased number of optimizations and directives offered by high-level synthesis tools to control the hardware generation process. One of the most explored optimizations is loop pipelining due to its impact on hardware throughput and resources. Nevertheless, the modulo scheduling algorithms used at resource-constrained loop pipelining are computationally expensive, and their application through the whole design space is often non-viable. Current state-of-the-art approaches rely on solving multiple optimization problems in polynomial time, or on solving one optimization problem in exponential time. This work proposes a novel data-flow-based approach, where exactly two optimization problems of polynomial time complexity are solved, leading to significant reductions on computation time for generating a single loop pipeline. Results indicate that, even for complex loops, the proposed method generates high-quality designs, comparable to the ones produced by existing state-of-the-art methods, achieving a reduction on the design-space exploration time by 2.46x (geomean). (AU) | |
| FAPESP's process: | 14/14918-2 - Code snippets identification for pipeline processing in FPGA accelerators for heterogeneous platforms |
| Grantee: | Leandro de Souza Rosa |
| Support Opportunities: | Scholarships in Brazil - Doctorate (Direct) |