SPHT: Scalable Persistent Hardware Transactions

Author(s)

Castro, Daniel ; Baldassin, Alexandro ; Barreto, Joao ; Romano, Paolo ; USENIX Assoc

• Document type: Journal article
• Source: PROCEEDINGS OF THE 19TH USENIX CONFERENCE ON FILE AND STORAGE TECHNOLOGIES (FAST '21); v. N/A, p. 15-pg., 2021-01-01.

Abstract

With the emergence of byte-addressable Persistent Memory (PM), a number of works have recently addressed the problem of how to implement persistent transactional memory using off-the-shelf hardware transactional memory systems. Using Intel Optane DC PM, we show, for the first time in the literature, experimental results highlighting several scalability bottlenecks of state of the art approaches, which so far have only been evaluated via PM emulation. We tackle these limitations by proposing SPHT (Scalable Persistent Hardware Transactions), an innovative Persistent Transactional Memory that exploits a set of novel mechanisms aimed at enhancing scalability both during transaction processing and recovery. We show that SPHT enhances throughput by up to 2.6x on STAMP and achieves speedups of up to 2.8x in the log replay phase vs. state of the art solutions. (AU)

• FAPESP's process: 19/10471-7 - Making the most out of hardware transactional memory
• Grantee: Alexandro José Baldassin
• Support Opportunities: Scholarships abroad - Research
• FAPESP's process: 18/15519-5 - Performance optimizations for multicore architectures
• Grantee: Alexandro José Baldassin
• Support Opportunities: Research Grants - Young Investigators Grants - Phase 2