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Using Multiple Abstraction Levels to Speedup an MPSoC Virtual Platform Simulator

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Author(s):
Moreira, Joao ; Klein, Felipe ; Baldassin, Alexandro ; Centoducatte, Paulo ; Azevedo, Rodolfo ; Rigo, Sandro ; IEEE
Total Authors: 7
Document type: Journal article
Source: 2011 22ND IEEE INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING (RSP); v. N/A, p. 7-pg., 2011-01-01.
Abstract

Virtual platforms are of paramount importance for design space exploration and their usage in early software development and verification is crucial. In particular, enabling accurate and fast simulation is specially useful, but such features are usually conflicting and tradeoffs have to be made. In this paper we describe how we integrated TLM communication mechanisms into a state-of-the-art, cycle-accurate, MPSoC simulation platform. More specifically, we show how we adapted ArchC fast functional instruction set simulators to the MPARM platform in order to achieve both fast simulation speed and accuracy. Our implementation led to a much faster hybrid platform, reaching speedups of up to 2.9x and 2.1x on average with negligible impact on power estimation accuracy (average 3.26% and 2.25% of standard deviation). (AU)

FAPESP's process: 09/04707-6 - Energy consumption analysis in STMs and a multicore simulation platform with hybrid abstraction
Grantee:João Batista Correa Gomes Moreira
Support Opportunities: Scholarships in Brazil - Master
FAPESP's process: 09/08239-7 - Energy Efficiency in Data Centers through Servers Modeling and Management
Grantee:Felipe Vieira Klein
Support Opportunities: Scholarships in Brazil - Post-Doctoral
FAPESP's process: 09/14681-4 - Exploiting parallelism in graphical user interfaces
Grantee:Alexandro José Baldassin
Support Opportunities: Scholarships in Brazil - Post-Doctoral