| Full text | |
| Author(s): |
Wachter, Eduardo
;
Erichsen, Augusto
;
Amory, Alexandre
;
Moraes, Fernando
;
Preas, K
Total Authors: 5
|
| Document type: | Journal article |
| Source: | DESIGN, AUTOMATION & TEST IN EUROPE; v. N/A, p. 6-pg., 2013-01-01. |
| Abstract | |
Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs. (AU) | |
| FAPESP's process: | 08/57870-9 - Critical Embedded Systems Institute |
| Grantee: | Jose Carlos Maldonado |
| Support Opportunities: | Research Projects - Thematic Grants |