Linearity Enhancement in Asymmetric Self-Cascode Composed by FD SOI nMOSFETs

Author(s)

Assalti, Rafael ; de Souza, Michelly ; Flandre, Denis ; IEEE

• Document type: Journal article
• Source: 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO); v. N/A, p. 4-pg., 2018-01-01.

Abstract

In this paper, the linearity of the Asymmetric Self-Cascode composed by Fully Depleted SOI nMOSFETs is experimentally evaluated, using transistors with different channel lengths. The abnormal (flat) transconductance of this composite transistor is used to promote a linearity enhancement. Disregarding the gain, the minimum harmonic distortion for low-power low-voltage applications has been obtained for the shortest transistor near the source and longest transistor near the drain. (AU)

• FAPESP's process: 15/08616-6 - Modeling, Simulation and Fabrication of Analog Circuits with Asymmetric Self-Cascode SOI Transistors
• Grantee: Rafael Assalti
• Support Opportunities: Scholarships in Brazil - Doctorate