Improving Transactional Code Generation via Variable Annotation and Barrier Elision

Author(s)

de Carvalho, Joao P. L. ; Honorio, Bruno C. ; Baldassin, Alexandro ; Araujo, Guido ; IEEE

• Document type: Journal article
• Source: 2020 IEEE 34TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM IPDPS 2020; v. N/A, p. 10-pg., 2020-01-01.

Abstract

With chip manufacturers such as Intel, IBM and ARM offering native support for transactional memory in their instruction set architectures, memory transactions are on the verge of being considered a genuine application tool rather than just an interesting research topic. Despite this recent increase in popularity on the hardware side of transactional memory (HTM), software support for transactional memory (STM) is still scarce and the only compiler with transactional support currently available, the GNU Compiler Collection (GCC), does not generate code that achieves desirable performance. This paper presents a detailed analysis of transactional code generated by GCC and by a proposed transactional memory support added to the Clang/LLVM compiler framework. Experimental results support the following contributions: (a) STM's performance overhead is due to an excessive amount of read and write barriers added by the compiler; (b) a new annotation mechanism for the Clang/LLVM compiler framework that aims to overcome the barrier over-instrumentation problem by allowing programmers to specify which variables should be free from transactional instrumentation; (c) a profiling tool that ranks the most accessed memory locations at runtime, working as a guiding tool for programmers to annotate the code. Furthermore, it is revealed that, by correctly using the annotations on just a few lines of code, it is possible to reduce the total number of instrumented barriers by 95% and to achieve speed-ups of up to 7x when compared to the original code generated by GCC and the Clang compiler. (AU)

• FAPESP's process: 19/04536-9 - Improving performance of collision cross section calculation through component annotation
• Grantee: Bruno Chinelato Honorio
• Support Opportunities: Scholarships in Brazil - Doctorate
• FAPESP's process: 13/08293-7 - CCES - Center for Computational Engineering and Sciences
• Grantee: Munir Salomao Skaf
• Support Opportunities: Research Grants - Research, Innovation and Dissemination Centers - RIDC
• FAPESP's process: 16/15337-9 - Distributed Transactional Memories and Efficient Data Distribution Models to Speed-up Irregular Data Structure Intensive Applications
• Grantee: João Paulo Labegalini de Carvalho
• Support Opportunities: Scholarships in Brazil - Doctorate
• FAPESP's process: 18/15519-5 - Performance optimizations for multicore architectures
• Grantee: Alexandro José Baldassin
• Support Opportunities: Research Grants - Young Investigators Grants - Phase 2