Recent microprocessors have incorporated transactions into their instruction set architecture (ISA). In this context, a transaction is a block of code that is executed in an all-or-nothing fashion, isolated from other transactions. Using the new ISA, programmers are allowed to delimit the instructions which make a transaction and the hardware is responsible to provide the transactional semantics. Most processors, however, provide transactions as a best-effort implementation, meaning that a transaction is not guaranteed to commit in hardware, thus relying on a fallback mechanism in software to decide on how to proceed. As a consequence, current research on transactional memory has focused on devising efficient hybrid (hardware/sofware) systems that can make the most out of current hardware support. This research project aims at investigating new opportunities to exploit hardware transactions, both in terms of performance and ease-of-use. The research shall be conducted in collaboration with researchers from INESC-ID/IST/ULisboa, Portugal. The investigation group at INESC-ID is leading the research on transactional memory in Europe, as demonstrated by the Euro-TM and Cloud-TM projects. The initial work plan is to integrate the hybrid PhTM* system, developed by this Proponent at UNESP, into the NV-HTM and DMP-TM systems, built at INESC-ID/IST/ULisboa, Portugal. Furthermore, this research project seeks to build and consolidate a strong collaboration with INESC-ID/IST/ULisboa, which will allow knowledge exchange between the institutions and also provide future students with a wider range of research and collaboration opportunities.
News published in Agência FAPESP Newsletter about the scholarship: