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Making the most out of Hardware Transactional Memory

Grant number: 19/10471-7
Support type:Scholarships abroad - Research
Effective date (Start): September 01, 2019
Effective date (End): August 31, 2020
Field of knowledge:Physical Sciences and Mathematics - Computer Science - Computer Systems
Principal Investigator:Alexandro José Baldassin
Grantee:Alexandro José Baldassin
Host: Joao Pedro Faria Mendonca Barreto
Home Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
Local de pesquisa : Universidade de Lisboa, Portugal  
Associated research grant:18/15519-5 - Performance optimizations for multicore architectures, AP.JP2

Abstract

Recent microprocessors have incorporated transactions into their instruction set architecture (ISA). In this context, a transaction is a block of code that is executed in an all-or-nothing fashion, isolated from other transactions. Using the new ISA, programmers are allowed to delimit the instructions which make a transaction and the hardware is responsible to provide the transactional semantics. Most processors, however, provide transactions as a best-effort implementation, meaning that a transaction is not guaranteed to commit in hardware, thus relying on a fallback mechanism in software to decide on how to proceed. As a consequence, current research on transactional memory has focused on devising efficient hybrid (hardware/sofware) systems that can make the most out of current hardware support. This research project aims at investigating new opportunities to exploit hardware transactions, both in terms of performance and ease-of-use. The research shall be conducted in collaboration with researchers from INESC-ID/IST/ULisboa, Portugal. The investigation group at INESC-ID is leading the research on transactional memory in Europe, as demonstrated by the Euro-TM and Cloud-TM projects. The initial work plan is to integrate the hybrid PhTM* system, developed by this Proponent at UNESP, into the NV-HTM and DMP-TM systems, built at INESC-ID/IST/ULisboa, Portugal. Furthermore, this research project seeks to build and consolidate a strong collaboration with INESC-ID/IST/ULisboa, which will allow knowledge exchange between the institutions and also provide future students with a wider range of research and collaboration opportunities.