Making the most out of hardware transactional memory

• Grant number: 19/10471-7
• Support Opportunities: Scholarships abroad - Research
• Start date: September 01, 2019
• End date: August 31, 2020
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Alexandro José Baldassin
• Grantee: Alexandro José Baldassin
• Host Investigator: João Pedro Faria Mendonça Barreto
• Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
• Institution abroad: Universidade de Lisboa, Portugal
• Associated research grant: 18/15519-5 - Performance optimizations for multicore architectures, AP.JP2

Abstract

Recent microprocessors have incorporated transactions into their instruction set architecture (ISA). In this context, a transaction is a block of code that is executed in an all-or-nothing fashion, isolated from other transactions. Using the new ISA, programmers are allowed to delimit the instructions which make a transaction and the hardware is responsible to provide the transactional semantics. Most processors, however, provide transactions as a best-effort implementation, meaning that a transaction is not guaranteed to commit in hardware, thus relying on a fallback mechanism in software to decide on how to proceed. As a consequence, current research on transactional memory has focused on devising efficient hybrid (hardware/sofware) systems that can make the most out of current hardware support. This research project aims at investigating new opportunities to exploit hardware transactions, both in terms of performance and ease-of-use. The research shall be conducted in collaboration with researchers from INESC-ID/IST/ULisboa, Portugal. The investigation group at INESC-ID is leading the research on transactional memory in Europe, as demonstrated by the Euro-TM and Cloud-TM projects. The initial work plan is to integrate the hybrid PhTM* system, developed by this Proponent at UNESP, into the NV-HTM and DMP-TM systems, built at INESC-ID/IST/ULisboa, Portugal. Furthermore, this research project seeks to build and consolidate a strong collaboration with INESC-ID/IST/ULisboa, which will allow knowledge exchange between the institutions and also provide future students with a wider range of research and collaboration opportunities. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

BALDASSIN, ALEXANDRO; BARRETO, JOAO; CASTRO, DANIEL; ROMANO, PAOLO. Persistent Memory: A Survey of Programming Support and Implementations. ACM COMPUTING SURVEYS, v. 54, n. 7, SEP 2021. (19/10471-7, 18/15519-5)

BALDASSIN, ALEXANDRO; MURARI, RAFAEL; DE CARVALHO, JOAO P. L.; ARAUJO, GUIDO; CASTRO, DANIEL; BARRETO, JOAO; ROMANO, PAOLO; MALAWSKI, M; RZADCA, K. NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory. EURO-PAR 2020: PARALLEL PROCESSING, v. 12247, p. 16-pg., 2020-01-01. (13/08293-7, 18/15519-5, 19/10471-7, 16/15337-9)

CASTRO, DANIEL; BALDASSIN, ALEXANDRO; BARRETO, JOAO; ROMANO, PAOLO; USENIX ASSOC. SPHT: Scalable Persistent Hardware Transactions. PROCEEDINGS OF THE 19TH USENIX CONFERENCE ON FILE AND STORAGE TECHNOLOGIES (FAST '21), v. N/A, p. 15-pg., 2021-01-01. (19/10471-7, 18/15519-5)