MOSFETs implemented with second generation gate layout styles to enhance electrical performance in extreme temperature environments, ionizing radiation, and external magnetic fields

• Grant number: 25/14715-9
• Support Opportunities: Scholarships in Brazil - Post-Doctoral
• Start date: September 01, 2025
• End date: September 30, 2027
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Measurements, Instrumentation
• Principal Investigator: Salvador Pinillos Gimenez
• Grantee: Egon Henrique Salerno Galembeck
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil
• Associated research grant: 24/14632-3 - MOSFETs implemented with second generation gate layout styles to enhance electrical performance in extreme temperature environments, ionizing radiation, and external magnetic fields., AP.R

Abstract

The search of developing new semiconductor devices that are even more robust and efficient to operate in extreme temperature environments, ionizing radiation, and under the influence of external magnetic fields (aerospace, medical, nuclear, automotive, military applications, etc.) is a significant challenge for the scientific community and companies that develop electronic equipment in all areas of human activity. Within this context, this research project aims to conduct a comparative study through three-dimensional numerical simulations and experimental data between the electrical performances of [Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs)] implemented with the so-called "Second Generation Gate Layout Styles for MOSFETs" (non-conventional hybrid gate geometries: Half-Diamond, Half-Octo, and Half-Ellipsoidal) and those implemented with conventional gate geometries counterpart. The study will investigate the effects of temperature (ranging from 100K to 573K), ionizing radiation from Total Ionizing Dose (TID), external magnetic fields on electrical performance, and the possibility of reducing the silicon area used by these transistors. This study is innovative, genuinely Brazilian, and will provide a low-cost alternative to further enhance the electrical performance of semiconductor devices produced with the current planar fabrication process of Complementary MOS (CMOS) integrated circuits. This provides numerous benefits to the semiconductor industry, such as reduced manufacturing costs, improved electrical performance, and increased transistor density per chip. Therefore, this study is fundamental to advancing semiconductor technology, as it offers an innovative solution to overcome miniaturization limitations (reduce the occupied silicon area by MOSFETs) and improve electrical performance in extreme environments of high temperatures, ionizing radiation, and external magnetic fields, driving technological advances in various sectors.