Full text
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| Author(s): |
Victor De Bodt Sivieri
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | São Paulo. |
| Institution: | Universidade de São Paulo (USP). Escola Politécnica (EP/BC) |
| Defense date: | 2016-02-26 |
| Examining board members: |
João Antonio Martino;
Aparecido Sirley Nicolett;
Sebastião Gomes dos Santos Filho
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| Advisor: | João Antonio Martino |
| Abstract | |
This Master thesis focused in the study of the NW-TFET. The study was performed either by simulation as by experimental measurements. The main digital and analog characteristics of the device and its potential for use in advanced integrated circuits for the next decade were studied. The analysis was performed by extracting and studying the devices main parameters, such as subthreshold swing, transconductance (gm), output conductance (gd), intrinsic voltage gain (AV) and transistor efficiency. The experimental measurements were compared with the results obtained by simulation. Utilizing different simulation fitting parameters and models, the device behavior (observed in the experimental measurements) was understood and explained. During the execution of this work, either the influence of the source material on the device performance, as the impact of the nanowire diameter on the transistor main analog parameters, were studied. The devices with SiGe source presented higher values of gm and gd than those with silicon source. The percentual difference among the values of transconductance for the different source materials varied from 43% to 96%, being dependent on the method utilized for the comparison, and the percentual difference among the values of output conductance varied from 38% to 91%. A degradation of AV was also observed with the nanowire diameter reduction. The gain calculated from the experimental measurements for the device with 50 nm of diameter is approximately 57% lower than the gain corresponding to the diameter of 110 nm. Furthermore, the impact of the diameter considering different gate biases (VG) was analysed. It was concluded that TFETs show improved performance for lower values of VG (a reduction of approximately 88% of AV was observed for an increase of the gate voltage from 1.25 V to 1.9 V). The gate/source overlap length and the dopant profile at the tunneling junction were also analyzed in order to understand which combination of this features would result in a better performance of the device. It was observed that the best results were related to an alignment between the gate electrode and the source/channel junction and to an abrupt dopant profile at the junction. Finally, the MOS technology was compared with TFET, resulting in a higher AV (higher than 40 dB) for the TFET. (AU) | |
| FAPESP's process: | 13/24472-9 - Study of Field Induced Tunneling Effect Transistor (Tunnel-FET) fabricated on Silicon Nanowire. |
| Grantee: | Victor de Bodt Sivieri |
| Support Opportunities: | Scholarships in Brazil - Master |