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A method to optimize performance/energy consumption relation for heterogeneous multi-core architectures on FPGA

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Bruno de Abreu Silva
Total Authors: 1
Document type: Doctoral Thesis
Press: São Carlos.
Institution: Universidade de São Paulo (USP). Instituto de Ciências Matemáticas e de Computação (ICMC/SB)
Defense date:
Examining board members:
Vanderlei Bonato; Rodolfo Jardim de Azevedo; Marcio Merino Fernandes; Wilian Soares Lacerda; Cláudio Fabiano Motta Toledo
Advisor: Vanderlei Bonato

Due to the growing need for high-performance computing along with higher volume of data to process, important changes are happening in computer architecture design. Parallel computing processors having hundreds or thousands of processing cores in a single chip are becoming a common solution, even for embedded systems. Power management becomes increasingly important, especially for mobile systems. A key challenge remaining open for these architectures is to perform the integration of application code, runtime scheduling and hardware control for power management. This thesis aims to present a method able to integrate these three aspects, by investigating techniques for optimizing performance versus power consumption in single-ISA heterogeneous multi-cores architectures implemented on FPGA. Our approach applies a data mining technique to analyze the application source-code, traditional techniques for power management, and an heterogeneity-aware scheduling policy. The main contributions are the combination of power management techniques at hardware, scheduling and compilation levels; a new scheduling policy along with a heterogeneous multi-core architecture relative to its L1 cache memory size determined offline and online. (AU)

FAPESP's process: 11/10163-9 - Power-performance optimization in hybrid reconfigurable multicore architectures
Grantee:Bruno de Abreu Silva
Support type: Scholarships in Brazil - Doctorate