Full text
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| Author(s): |
Carlos Augusto Bergfeld Mori
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | São Paulo. |
| Institution: | Universidade de São Paulo (USP). Escola Politécnica (EP/BC) |
| Defense date: | 2018-02-09 |
| Examining board members: |
João Antonio Martino;
Victor Sonnenberg;
Gilson Inácio Wirth
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| Advisor: | João Antonio Martino; Paula Ghedini Der Agopian |
| Abstract | |
Due to the reduction of devices\' dimensions and the use of new materials with low thermal conductivity, self-heating affects the performances of advanced transistors. Devices under self-heating effects suffer an increase of their temperature, causing mobility reduction, besides compromising reliability and generating signal delays, bringing impacts to the efficiency of analog circuits, and affecting the performance of digital circuits. Despite the relevance of the phenomenon, many studies do not consider it, given the difficulty to assess it, since the methods used for advanced transistors require special structures or equipment, which are rarely available. Hence, three new techniques are developed in this work, with the objective of permitting the study of the effect utilizing conventional structures and direct current measurements: (i) the mean output conductance method; (ii) the signature in the transistor efficiency method; (iii) the thermal resistance estimative using only direct current measurements. The first two methods are focused on a qualitative analysis of the self-heating, allowing an efficient preliminary verification of the presence and relevance of the effect, while the last allows the extraction of the thermal resistance from the inverse of the transistor efficiency through an iterative process, consequently making it possible to obtain the temperature rise in the channel due to the self-heating with a good precision and greater simplicity when compared to other methods available in the literature (with maximum error smaller than 6% for multiple gate transistors when compared to the pulsed method). With these techniques, comparisons between multiple gate transistors (also known as FinFET or 3D transistors) and silicon-on-oxide with ultra-thin body and buried oxide (SOI UTBB) are performed, utilizing three-dimensional simulations to obtain similar power conditions. In devices with smaller channel length, FinFETs presented temperatures approximately 60 K above the UTBBs. (AU) | |
| FAPESP's process: | 15/25101-0 - Comparative study of the self-heating effect on FinFET and SOI UTBB transistors |
| Grantee: | Carlos Augusto Bergfeld Mori |
| Support Opportunities: | Scholarships in Brazil - Master |