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Study and analysis of compact models for UTBB SOI MOSFETs

Grant number: 14/11627-7
Support type:Scholarships abroad - Research Internship - Doctorate
Effective date (Start): October 01, 2014
Effective date (End): March 31, 2015
Field of knowledge:Engineering - Electrical Engineering
Principal Investigator:Renato Camargo Giacomini
Grantee:Arianne Soares Do Nascimento Pereira
Supervisor abroad: Denis Flandre
Home Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil
Local de pesquisa : Universitè Catolique de Louvain (UCL), Belgium  
Associated to the scholarship:12/12700-4 - Analytical models for static electric behaviour of FinFETs, BP.DR

Abstract

SOI (Silicon-On-Insulator) technology emerged aiming to answer for the demand ofintegrated circuit technologies that could allow the reduction of transistor dimensions beyondthe limits of bulk technology. The Ultra-Thin Body and Buried oxide (UTBB) SOI transistor, as well as the FinFETs (multiple gates),is now considered as an actual alternative to standard CMOS for 20nm node and below, dueto its better electrostatic control. Besides, the UTBB devices allow both low power and highperformance circuits in the same chip, thanks to the multiple threshold voltages achieved bydifferent back-gate biases.Compact models are important tools for understanding the devices behavior andfurther the technology prediction. Accurate and computationally efficient compact models forultra-scaled transistors have to be developed and improved, in order to efficiently design andsimulate complex application circuits. For UTBB devices, there are some models in literaturethat take into account the independent gate operation of ultra-thin devices. Up to now, thereare two compact models already implemented in circuit simulators that have been indicatedfor the use in UTBB devices: the BSIM-IMG model, from Berkeley University and theUTSOI2 model, from CEA-LETI and STMicroelectronics.This research project aims at evaluating the application of these compact models toUTBB devices. The models behavior will be studied from experimental data and devicesimulation. Hence, it will be possible to propose improvements for the models, with betterphysics description, considering specific effects of UTBB devices.The results will be evaluated with device simulations, experimental data fromliterature and experimental data from UTBB devices that are available at UCL, where theresearch will be developed. A critical review of achieved results will be made, in order toposition them in the international context of the research area, and opportunely published. (AU)

Scientific publications
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
PEREIRA, A. S. N.; DE STEEL, G.; PLANES, N.; HAOND, M.; GIACOMINI, R.; FLANDRE, D.; KILCHYTSKA, V. An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models. Solid-State Electronics, v. 128, n. SI, p. 67-71, FEB 2017. Web of Science Citations: 2.

Please report errors in scientific publications list by writing to: cdi@fapesp.br.