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| Author(s): |
Andre Luis Rodrigues Mansano
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | Campinas, SP. |
| Institution: | Universidade Estadual de Campinas (UNICAMP). Faculdade de Engenharia Elétrica e de Computação |
| Defense date: | 2009-12-17 |
| Examining board members: |
Jacobus Willibrordus Swart;
Sandro Augusto Pavlik Haddad;
Fabiano Fruett
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| Advisor: | Jader Alves Lima Filho; Jacobus Willibrordus Swart |
| Abstract | |
In this work, a DC/DC charge-pump voltage-doubler converter, for maximum load current of 20mA, was designed and fabricated. The Charge Pump (CP) needs control circuits for properly switching, voltage regulation and protection of voltage doubler stage. The control system designed comprises a linear regulation circuit (CRL), a Skip mode regulator, current limitation circuit (LC) and a bootstrapping circuit (BOOT), which provides the appropriate voltage to turn on CP power transistors. The voltage doubler is the power stage that interfaces directly to the load and its nominal input voltage PVIN is 1.5V. The objective of this work is to guarantee that the proposed DC/DC converter works properly (proved by Silicon results) and to achieve experimental results with the least deviation possible compared to simulation. The nominal output voltage (VOUT) with no load is 3V. For maximum DC load (20mA), simulated VOUT is 2.4V. BOOT circuit provides voltage within 4.5V - 5V for DC current load of 1mA. The LC limits the drawn current through the voltage-doubler at 30mA. The CRL provides a control voltage inversely proportional to VOUT and its minimum and maximum are 1.3V and 5.2V respectively. The whole system has been integrated in AMS 0.35um HV except the capacitors of CP and BOOT circuits. The experimental results show deviation (comparing to simulation) of -12,5% on VOUT @ 20mA DC and -0,13% @ no load , -6% on BOOT output @ 1mA DC, +23% CLR minimum, -3,85% CRL maximum and +10% on LC circuit. During the development of this work, the CRL circuit has been published in the SBCCI 2009 conference to present its fast-response to stringent load transient which is the biggest CRL advantage compared to previously proposed circuits (AU) | |