Full text
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| Author(s): |
Erinaldo da Silva Pereira
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | São Carlos. |
| Institution: | Universidade de São Paulo (USP). Instituto de Ciências Matemáticas e de Computação (ICMC/SB) |
| Defense date: | 2014-06-09 |
| Examining board members: |
Eduardo Marques;
Vanderlei Bonato;
Pedro Nuno Cruz Diniz
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| Advisor: | Eduardo Marques |
| Abstract | |
This work presents the development of an open source based Nios II processor from Altera. The developed processor allows custom instructions, use of components that allows a detailed study of the cache memory, among other features. In addition, the processor is based on the Nios II architecture, which can be integrated into the Qsys and SOPC Builder of the Altera Quartus II environment tool as well as use the entire set of IP (Intellectual Property) and tools available from Altera. This work contributes to the development of hardware architectures with a processing unit configurable and easily customizable by the user, since its source code in Bluespec SystemVerilog is open to all users, other than the Nios II from Altera which has encrypted code, making it impossible to do any changes in the processor at RTL (Register Transfer level) level. For the development of the processor hardware the description language Bluespec SystemVerilog was used, which is an ESL (Electronic System Level) that speeds up the development of the hardware (AU) | |
| FAPESP's process: | 11/15319-7 - Design of an open-source processor in Bluespec Based on Soft-core processor from Altera Nios II |
| Grantee: | Erinaldo da Silva Pereira |
| Support Opportunities: | Scholarships in Brazil - Master |