A method to accelerate floating point algorithms in FPGAs

• Grant number: 14/20835-2
• Support type: Scholarships in Brazil - Scientific Initiation
• Effective date (Start): January 01, 2015
• Effective date (End): December 31, 2015
• Field of knowledge: Physical Sciences and Mathematics - Computer Science
• Principal Investigator: Ricardo Menotti
• Grantee: Leonardo Henrique Benedette Lopes
• Home Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos, SP, Brazil

Abstract

FPGAs have proven to be efficient in terms of performance and power consumption for numerous applications, both in embedded systems and high performance computing. The main challenge for the more intensive use of this technology is the difficulty in programming these devices. To mitigate this problem, various applications are implemented in software using hardware executing on critical sections. The density of current FPGAs allows the implementation of complex applications. The aim of this research is to develop a methodology to accelerate floating-point algorithms in FPGAs. From a chosen benchmark, we will identify critical sections of the application and implement then in dedicated hardware, integrating into the original software. The study will examine how best integrate software and hardware, implementing accelerators connected to the bus. The initial validation platform of the methodology will be based on the Altera DE2-115 FPGA kit, using the VHDL language and the Altera Quartus II tool. Nios II processor will be adopted as a software platform, for its ease of use and integration with other tools. It is expected to apply the methodology for at least two applications with different characteristics. At the end of the project, is expected to draw up a detailed roadmap of the methodology, highlighting the critical points.