An accelerator for deep neural convolutional networks implemented in FPGA

• Grant number: 17/13520-3
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: September 01, 2017
• End date: January 01, 2019
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Ricardo Menotti
• Grantee: Leonardo Tavares Oliveira
• Host Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos , SP, Brazil
• Associated scholarship(s): 18/00096-1 - Implementation of a convolutional layer using approximate multipliers in FPGA for convolutional neural networks, BE.EP.IC

Abstract

With the evolution of High Performance Computing (HPC) began the popularization of many programs and algorithms that required high computational power, for example the deep neural convolutional network(DNCN). The DNCN, that are mostly used for image classification and recognition, achieved a peak of popularity with the triumph of the AlexNet in the ImageNet Large Scale Visual Recognition Competition of 2010, having acquired 17.0% correct classification in Top 5. Further more, the use of FPGAs for the acceleration of highly parallel programs became an essential part of HPC, allowing the creation of specific hardware (higher performance) with decreased energy consumption. With this being said, this project aims to use the high capacity of parallelization of DNCNs to implement its core layers in FPGA, creating an architeture for its training and using in hardware. (AU)