Alexandro José Baldassin
CV Lattes
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Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Instituto de Geociências e Ciências Exatas (IGCE) (Institutional affiliation for the last research proposal) Birthplace: Brazil
bachelor's at Bacharelado em Ciências da Computação from Universidade Estadual Paulista - Júlio de Mesquita Filho (2002), master's at Computer Science from Universidade Estadual de Campinas (2004) and doctorate at Computer Science from Universidade Estadual de Campinas (2009). Has experience in Computer Science, focusing on Computer Systems Architecture, acting on the following subjects: inteligencia artificial, retargetable tools, platform debugging, agentes inteligentes and filtragem de informacao. (Source: Lattes Curriculum)
- Performance optimizations for multicore architectures, AP.JP2
Abstract
Multicore machines are ubiquitous nowadays and the tendency is for semiconductor companies to keep adding more and more cores into their new microprocessors. Unfortunately, support for programming these highly parallel machines have not kept pace and we are left with underutilized computer systems. The big challenge facing the industry today is how to ease the life of programmers in wri...
- Understanding and exploiting energy/performance tradeoffs in concurrent algorithms, AP.JP
Abstract
Microarchitectural limitations and high energy dissipation have forced the semiconductor industry to shift from single-core processors to multicores. This new approach allows the transistor growth foresaw by Moore's law to continue but, instead of increasing the clock frequency and exploiting instruction level parallelism, more cores are being integrated into a single die. This shift ha...
- Integrating speculative execution to loop and Task-based parallelization, BP.PD
Abstract
This proposal brings five contributions to address code parallelization. First, it proposes a tool to measure the loop-carried probability of each component of a loop and to detect loop-carried patterns in the loop extending the OpenMP check clause. Initial experiments shows that loop-carried probability is an effective metric to decide when to use TLS or BDX to parallelize loops, thus,...
- Scheduling threads and pages on NUMA systems, BP.MS
Abstract
Assigning threads and memory pages to nodes of a NUMA architecture in a way that matches the demand for remote data transfers with the available communication bandwidths and memory-controller capacity in the machine can have a significant impact in the execution time of programs. Such assignment typically requires dealing with four simultaneous goals: (a) keep threads close to the memor...
- Improving performance and debugging of transactional applications through programmer annotations, BP.MS
Abstract
Transactional Memory (TM) allows programmers to use the concept of transaction while writing concurrent code. In this context, a transaction may be understood as a block of instructions that is executed atomically and in isolation, that is, each transaction intermediate processing states are not visible to the others. Although initially confined to the academic environment, TM is quickl...
- Using hardware transactional support to accelerate software transactional memory systems, BP.MS
Abstract
The limited performance gain due to micro-architectural optimizations and the modest increase in clock rate led the microprocessor industry to seek alternatives to single-core processors in order to keep up with the performance demand. The solution found was to build architectures with multiple execution flows (multicore). Nonetheless, the parallel model immediate adoption requires prog...
(Only some records are available in English at this moment)
- Making the most out of Hardware Transactional Memory, BE.PQ
Abstract
Recent microprocessors have incorporated transactions into their instruction set architecture (ISA). In this context, a transaction is a block of code that is executed in an all-or-nothing fashion, isolated from other transactions. Using the new ISA, programmers are allowed to delimit the instructions which make a transaction and the hardware is responsible to provide the transactional...
- Scheduling threads and pages in numa systems, BE.EP.MS
Abstract
Assigning threads and memory pages to nodes of a NUMA architecture in a way that matches the demand for remote data transfers with the available communication bandwidths and memory-controller capacity in the machine can have a significant impact in the execution time of programs. Such assignment typically requires dealing with four simultaneous goals: (a) keep threads close to the memor...
| 1 / 1 | Ongoing research grants |
| 2 / 1 | Completed research grants |
| 1 / 1 | Ongoing scholarships in Brazil |
| 9 / 7 | Completed scholarships in Brazil |
| 1 / 1 | Ongoing scholarships abroad |
| 1 / 1 | Completed scholarships abroad |
| 15 / 12 | All research grants and scholarships |
| Associated processes | |
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
| Publications | 3 |
| Citations | 11 |
| Cit./Article | 3.7 |
| Data from Web of Science | |
BALDASSIN, ALEXANDRO; GOLDSTEIN, FELIPE; AZEVEDO, RODOLFO. A transactional runtime system for the Cell/BE architecture. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, v. 72, n. 12, p. 1535-1546, DEC 2012. Web of Science Citations: 2. (11/19373-6)
BALDASSIN, ALEXANDRO; BORIN, EDSON; ARAUJO, GUIDO. Performance Implications of Dynamic Memory Allocators on Transactional Memory Systems. ACM SIGPLAN NOTICES, v. 50, n. 8, p. 87-96, AUG 2015. Web of Science Citations: 3. (11/19373-6)
NICACIO, DANIEL; BALDASSIN, ALEXANDRO; ARAUJO, GUIDO. Transaction Scheduling Using Dynamic Conflict Avoidance. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, v. 41, n. 1, p. 89-110, FEB 2013. Web of Science Citations: 6. (11/19373-6)
(References retrieved automatically from State of São Paulo Research Institutions)
CARVALHO, João Paulo Labegalini de. PhTM* : uma implementação eficiente de transações em fases. 2016. 60f. Dissertação (Mestrado) - . Universidade Estadual Paulista "Júlio de Mesquita Filho" Instituto de Biociências (Campus de Rio Claro). (14/00534-8)
LEITE, Gustavo. Performance evaluation of code optimizations in FPGA accelerators. 2019. Dissertação (Mestrado) - . Universidade Estadual Paulista "Júlio de Mesquita Filho" Instituto de Biociências, Letras e Ciências Exatas. (17/09065-9)
HONORIO, Bruno Chinelato. Melhorando o desempenho de aplicações transacionais através de anotações do programador. 2018. 53f. Dissertação (Mestrado) - . Universidade Estadual Paulista "Júlio de Mesquita Filho" Instituto de Biociências, Letras e Ciências Exatas. (16/12103-7)