| Full text | |
| Author(s): |
Baldassin, Alexandro
[1]
;
Barreto, Joao
[2, 3, 4]
;
Castro, Daniel
[2, 3, 4]
;
Romano, Paolo
[2, 3, 4]
Total Authors: 4
|
| Affiliation: | [1] Sao Paulo State Univ Unesp, Inst Geosci & Exact Sci, Ave 24A, 1515, BR-13506900 Sao Paulo - Brazil
[2] Univ Lisbon, Inst Super Tecn, INESC ID, Lisbon - Portugal
[3] Univ Lisbon, INESC ID, Rua Alves Redol 9, P-1000029 Lisbon - Portugal
[4] Univ Lisbon, Inst Super Tecn, Rua Alves Redol 9, P-1000029 Lisbon - Portugal
Total Affiliations: 4
|
| Document type: | Journal article |
| Source: | ACM COMPUTING SURVEYS; v. 54, n. 7 SEP 2021. |
| Web of Science Citations: | 0 |
| Abstract | |
The recent rise of byte-addressable non-volatile memory technologies is blurring the dichotomy between memory and storage. In particular, they allow programmers to have direct access to persistent data instead of relying on traditional interfaces, such as file and database systems. However, they also bring new challenges, as a failure may render the program in an unrecoverable and inconsistent state. Consequently, a lot of effort has been put by both industry and academia into making the task of programming with such memories easier while, at the same time, efficient from the runtime perspective. This survey summarizes such a body of research, from the abstractions to the implementation level. As persistent memory is starting to appear commercially, the state-of-the-art research condensed here will help investigators to quickly stay up to date while also motivating others to pursue research in the field. (AU) | |
| FAPESP's process: | 19/10471-7 - Making the Most out of Hardware Transactional Memory |
| Grantee: | Alexandro José Baldassin |
| Support type: | Scholarships abroad - Research |
| FAPESP's process: | 18/15519-5 - Performance optimizations for multicore architectures |
| Grantee: | Alexandro José Baldassin |
| Support type: | Research Grants - Young Investigators Grants - Phase 2 |