| Full text | |
| Author(s): |
de Souza, Michelly
;
Rodrigues, Jaime Calcade
;
Mariniello, Genaro
;
Casse, Mikael
;
Barraud, Sylvain
;
Vinet, Maud
;
Faynot, Olivier
;
Pavanello, Marcelo A.
;
IEEE
Total Authors: 9
|
| Document type: | Journal article |
| Source: | 2022 IEEE 15TH WORKSHOP ON LOW TEMPERATURE ELECTRONICS (WOLTE 2022); v. N/A, p. 4-pg., 2022-01-01. |
| Abstract | |
In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry. (AU) | |
| FAPESP's process: | 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties |
| Grantee: | Marcelo Antonio Pavanello |
| Support Opportunities: | Regular Research Grants |