Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

Author(s)

de Souza, Michelly ; Cerdeira, Antonio ; Estrada, Magali ; Barraud, Sylvain ; Casse, Mikael ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo A. ; IEEE

• Document type: Journal article
• Source: 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC); v. N/A, p. 4-pg., 2022-01-01.

Abstract

This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one. (AU)

• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants