| Full text | |
| Author(s): |
Baldassin, Alexandro
;
Murari, Rafael
;
de Carvalho, Joao P. L.
;
Araujo, Guido
;
Castro, Daniel
;
Barreto, Joao
;
Romano, Paolo
;
Malawski, M
;
Rzadca, K
Total Authors: 9
|
| Document type: | Journal article |
| Source: | EURO-PAR 2020: PARALLEL PROCESSING; v. 12247, p. 16-pg., 2020-01-01. |
| Abstract | |
Non-Volatile Memory (NVM) is an emerging memory technology aimed to eliminate the gap between main memory and stable storage. Nevertheless, today's programs will not readily benefit from NVM because crash failures may render the program in an unrecoverable and inconsistent state. In this context, durable transactions have been proposed as a mechanism to ease the adoption of NVM by simplifying the task of programming NVM systems. Existing systems employ either hardware (HW) or software (SW) transactions with different performance tradeoffs. Although SW transactions are flexible and unbounded, they may significantly hurt the performance of short-lived transactions. On the other hand, LIW transactional memories provide low-overhead but are resource-constrained. In this paper we present NV-PhTM, a transactional system for NVM that delivers the best out of both LIW and SW transactions by dynamically selecting the best execution mode according to the application's characteristics. NV-PhTM is comprised of a set of heuristics to guide online phase transition while retaining persistency in case of crashes during migration. To the best of our knowledge, NV-PhTM is the first phase-based system to provide durable transactions. Experimental results with the STAMP benchmark show that the proposed heuristics are efficient in guiding phase transitions with low overhead. (AU) | |
| FAPESP's process: | 13/08293-7 - CCES - Center for Computational Engineering and Sciences |
| Grantee: | Munir Salomao Skaf |
| Support Opportunities: | Research Grants - Research, Innovation and Dissemination Centers - RIDC |
| FAPESP's process: | 18/15519-5 - Performance optimizations for multicore architectures |
| Grantee: | Alexandro José Baldassin |
| Support Opportunities: | Research Grants - Young Investigators Grants - Phase 2 |
| FAPESP's process: | 19/10471-7 - Making the most out of hardware transactional memory |
| Grantee: | Alexandro José Baldassin |
| Support Opportunities: | Scholarships abroad - Research |
| FAPESP's process: | 16/15337-9 - Distributed Transactional Memories and Efficient Data Distribution Models to Speed-up Irregular Data Structure Intensive Applications |
| Grantee: | João Paulo Labegalini de Carvalho |
| Support Opportunities: | Scholarships in Brazil - Doctorate |