Zero Temperature Coefficient Study Regarding the Half-Diamond Layout Style for MOSFETs

Author(s)

Peixoto, M. A. P. ; Braga de Lima, M. P. ; Galembeck, E. H. S. ; Correia, M. M. ; Camillo, L. M. ; Gimenez, S. P.

• Document type: Journal article
• Source: 2024 38TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES, SBMICRO 2024; v. N/A, p. 4-pg., 2024-01-01.

Abstract

This paper studies the behavior of the Zero Temperature Coefficient (ZTC) of the first element of the second generation of the gate layout styles for MOSFETs, the Half-Diamond MOSFET (HDM). This work was performed based on three-dimensional (3D) numerical simulations (3D-NS) initially fitted by experimental data at room temperature. Camillo-Martino ZTC analytical model (CM-Model) application demonstrated a good agreement (maximum error of 5.9% above 400K) with the simulations in predicting the ZTC point behavior of a Bulk HDM for high temperatures. (AU)

• FAPESP's process: 20/09375-0 - Design and interactive optimization tool for integrated circuits based on computational intelligence
• Grantee: Rodrigo Alves de Lima Moreto
• Support Opportunities: Research Grants - Innovative Research in Small Business - PIPE