Analysis of a low-dropout voltage regulator designed using omega-gate nanowire transistors experimental data.

Author(s)

Penna da Silval, Pedro H. ; Martino, Joao A. ; Agopian, Paula G. D.

• Document type: Journal article
• Source: 2024 38TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES, SBMICRO 2024; v. N/A, p. 4-pg., 2024-01-01.

Abstract

In this work, the low-dropout voltage regulator (LDO) was designed using omega-gate nanowire transistors. These transistors were modeled using the Verilog-A description based on the experimental data. After the model validation LDO's were developed using gm/I-D strategy considering transconductance over drain current ratio (gm/I-D) of 7V(-1) and 8V(-1) with load capacitances of 10pf and 100pf. The LDO was designed to provide a voltage of 1.5V and 100 mu A at the output. The LDO biased transistors with gm/I-D equal to 8V(-1) presented very good results where the Loop Voltage Gain was 52.2dB, the gain bandwidth product (GBW) was 5.9MHz for load of 10pf, the load regulation was 27V/A and power supply rejection (PSR) was 41dB showing that Omega-gate nanowire transistors can be a good option for LDOs circuits. (AU)

• FAPESP's process: 20/04867-2 - High energy physics and instrumentation with the LHC-CERN
• Grantee: Marcelo Gameiro Munhoz
• Support Opportunities: Special Projects