| Full text | |
| Author(s): |
Martino, Joao Antonio
;
Agopian, Paula Ghedini Der
;
de Paula, Julius Andretti Peixoto Pires
;
Ritzenthaler, Romain
;
Mertens, Hans
;
Veloso, Anabela
;
Horiguchi, Naoto
Total Authors: 7
|
| Document type: | Journal article |
| Source: | Solid-State Electronics; v. 227, p. 4-pg., 2025-04-24. |
| Abstract | |
This work presents an experimental study of the analog behavior of forksheet FET from room up to 150 degrees C with channel lengths of 26 and 70 nm. These devices present a Zero Temperature-Coefficient (ZTC) point for a gate voltage around 0,59 V (VZTC) in saturation region. The threshold voltage variation with temperature (dVT/dT) is around - 0,5mV/oC due to the Fermi level decrease. The DIBL increases with temperature but it is kept lower than 51 mV/V in the studied temperature range. The transconductance and output conductance decrease (mainly due the mobility degradation) which results in a good intrinsic voltage gain of around 36 dB at room temperature, showing a slight change (+/- 2dB) in the studied temperature range. The maximum unity gain frequency estimated for L = 26 nm is around 358 GHz in strong inversion regime. The results show that the forksheet FETs present a good performance for analog applications at high temperature, which in addition to the already known savings in footprint area compared to nanosheet technology, are potentially useful for future mixed-signal integrated circuits. (AU) | |
| FAPESP's process: | 20/04867-2 - High energy physics and instrumentation with the LHC-CERN |
| Grantee: | Marcelo Gameiro Munhoz |
| Support Opportunities: | Special Projects |