| Full text | |
| Author(s): |
Baldassin, Alexandro
[1]
;
Klein, Felipe
[1]
;
Araujo, Guido
[1]
;
Azevedo, Rodolfo
[1]
;
Centoducatte, Paulo
[1]
Total Authors: 5
|
| Affiliation: | [1] Univ Estadual Campinas, Inst Comp, Campinas, SP - Brazil
Total Affiliations: 1
|
| Document type: | Journal article |
| Source: | IEEE COMPUTER ARCHITECTURE LETTERS; v. 8, n. 2, p. 56-59, JUL-DEC 2009. |
| Web of Science Citations: | 3 |
| Abstract | |
The well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for concurrent execution, of which transactional memory is a promising one. Extensive research has been carried out on Software Transaction Memory (STM), most of all concentrated on program performance, leaving unattended other metrics of great importance like energy consumption. This letter presents a thorough evaluation of energy consumption in a state-of-the-art STM. We show that energy and performance results do not always follow the same trend and, therefore, it might be appropriate to consider different strategies depending on the focus of the optimization. We also introduce a novel strategy based on dynamic voltage and frequency scaling for contention managers, revealing important energy and energy-delay product improvements in high-contended scenarios. This work is a first study towards a better understanding of the energy consumption behavior of STM systems, and could prompt STM designers to research new optimizations in this area, paving the way for an energy-aware transactional memory. (AU) | |
| FAPESP's process: | 05/02565-9 - Power analysis/optimization of heterogeneous SoCs weighting hardware/software components |
| Grantee: | Felipe Vieira Klein |
| Support Opportunities: | Scholarships in Brazil - Doctorate |