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| Author(s): |
Cristiano Bacelar de Oliveira
Total Authors: 1
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| Document type: | Doctoral Thesis |
| Press: | São Carlos. |
| Institution: | Universidade de São Paulo (USP). Instituto de Ciências Matemáticas e de Computação (ICMC/SB) |
| Defense date: | 2015-12-21 |
| Examining board members: |
Eduardo Marques;
Edson Borin;
João Manuel Paiva Cardoso;
Pedro Nuno Cruz Diniz;
Marcio Merino Fernandes
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| Advisor: | Eduardo Marques; João Manuel Paiva Cardoso |
| Abstract | |
Considering the demand for high-performance in computer systems, the implementation of algorithms directly in hardware by using FPGAs (Field-programmable Gate Arrays) is an alternative that has shown good results. However, the number of developers is limited due to the challenges faced for efficiently programming FPGAs. In addition to that, developers are more used to the traditional sequential programming paradigm imposed by the imperative languages. This work seeks to develop mechanisms to facilitate the development with FPGAs, by optimizing memory usage and exploiting the parallelism of operations inside a loop. This document presents the doctoral thesis entitled LALP+ : a framework for developing FPGA-based hardware accelerators. Since the latency for reading and writing data have been a bottleneck for high performance applications, this work deals with the development of techniques for generation of hardware architectures, considering aspects related to mapping, management and memory access in reconfigurable architectures, using as basis the LALP language, which focuses on the treatment of loops with the technique of loop pipelining. The techniques described in this thesis are employed in the development of the LALP+ framework, which extends LALP by implementing new features and functionalities, in order to contribute to increase its abstraction level. LALP+ architectures were compared to ones generated by using academical and commercial tools, having presented, on average, better performance, with a execution time speedup of 10;01 for the best case. Thus, it is expected that the hereby presented contributions facilitate the implementation of products and projects related to high-performance computing applications with reconfigurable architectures, contributing for the use of such technology. (AU) | |
| FAPESP's process: | 11/11040-8 - Combining data and computation transformations for Fine-grain reconfigurable architectures |
| Grantee: | Cristiano Bacelar de Oliveira |
| Support Opportunities: | Scholarships in Brazil - Doctorate |