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| Author(s): |
Katia Regina Akemi Sasaki
Total Authors: 1
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| Document type: | Doctoral Thesis |
| Press: | São Paulo. |
| Institution: | Universidade de São Paulo (USP). Escola Politécnica (EP/BC) |
| Defense date: | 2016-11-17 |
| Examining board members: |
João Antonio Martino;
Marco Isaías Alayo Chávez;
Fabiano Fruett;
Salvador Pinillos Gimenez
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| Advisor: | João Antonio Martino |
| Abstract | |
In this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal-Oxide- Semiconductor Field-Effect-Transistor), operating in conventional (VB=0V), dynamic threshold (DT2-UTBB, where the back-gate bias is equal to the front-gate one, VB=VG) and enhanced DT (kDT-UTBB, where the back-gate bias is a multiple value of the front-gate one, VB=kVG) modes. The working principle of these modes has been studied and the effect of different technologies and current trends were analyzed under such biasing conditions as the presence of the ground plane (ground plane - GP), the scaling of the silicon layer and the absence of a doped extended source and drain region. It was also proposed in this paper the inverse kDT-UTBB mode, where the gate voltage is a multiple of the back-gate one (VB=kVG). The supercoupling effect was identified and analyzed through different techniques, such as the capacitance curves, its influence on the body effect and in UTBB SOI transistors operating in DT2 and kDT modes. Finally, the high temperature influence was also studied in UTBB SOI transistors operating in DT2 and kDT modes, as well as on capacitance characteristics. The operation DT2 showed better results than the conventional method, mainly for shorter channels (reduced subthreshold slope, SS, in 36%, increased maximum transconductance, gm,max, in 23% and reduced Drain Induced Barrier Lowering, DIBL, 57%). The presence of GP intensified this improvement (reducing SS by 51%, raising gm,max by 32% and reduced DIBL by 100%), due to the greater coupling of the substrate on the channel, strengthening its influence on reducing the threshold voltage. The kDT mode showed better electrical parameters than the DT2 due to a remarkable reduction of the threshold voltage for the same VG sweep. In the inverse kDT mode, the parameters were also better (60% lower SS and 147% higher gm,max for devices without GP and 68% lower SS and 189% higher gm,max on devices with GP) due to the thinner gate oxide than the buried oxide. With regard to the silicon film scaling, for higher values of gate voltage, the thinner silicon layer presented a larger series resistance and a greater mobility degradation, reducing the drain current. For negative gate biases, the GIDL (Gate Induced Drain Leakage) is higher for smaller thicknesses of the silicon film. However, the lower silicon film thickness showed to be advantageous in kDT due to the stronger coupling. The thinner silicon thickness has improved the DIBL (thickness of 6nm presented a DIBL 3 times smaller than the device of 14nm for k = 5), reducing the drain electric field, and the SS (thickness of 6nm presented an SS 7% smaller than 14nm device for k = 5), where the vertical electric field is not enough to degrade the device parameter. The supercoupling demonstrated beneficial results in UTBB transistors in DT2 and kDT operations, amplifying the volume inversion effect and rising significantly the transconductance and the mobility (improvement of up to 131% for k=5, 7nm-NMOS, taking VB=0V as the reference). Measurements and simulations have also shown positive results in the scalability study, presenting an excellent coupling for the shortest channel considered (0.076 for L=20nm against 0.09 for L=1µm). With respect to source and drain engineering, the best results were obtained for devices without the extension implantation and spacer length of 20nm. They also demonstrated to be more susceptible to the increase of k factor, showing the best behavior in the subthreshold region (59% lower), analog performance (300% higher intrinsic voltage gain, AV and 600% higher Early voltage, VEA) and for low voltages applications (reduced SS and VT). The only drawback observed for operation in kDT was the higher GIDL current (increase of 1 order of magnitude between self-aligned transistors with k=5 and self-aligned ones with k=0). However, the devices without the extension region implantation had a lower GIDL (1 order of magnitude lower for 20nm-extensionless devices with k=5, taking the self-aligned ones with k=5 as the reference) due to the lower gate-to-drain electric field, which can be a solution to this disadvantage. The longer extension region (without implantation) and, mainly, the kDT operation improved the parameters (increase of 82% in gm,max, reduction of 45% in SS, 41% reduced DIBL, rising of 303% in AV and 97% increased VEA), surpassing the degradation caused by rising the temperature (the last percentages is already considering the temperature degradation). Moreover, the DT2 and kDT operations reduced the gate bias of the ZTC point (Zero-Temperature-Coefficient) in 57%, being interesting for low voltage applications. The kDT mode also allowed the threshold voltage and the biases tunning, still with the current level independent of the temperature and the k-factor. (AU) | |
| FAPESP's process: | 13/13690-5 - Study of SOI MOSFETs transistors with ultra-thin silicon film body and buried oxide at high temperatures |
| Grantee: | Katia Regina Akemi Sasaki |
| Support Opportunities: | Scholarships in Brazil - Doctorate |